Silicon MLOps Qualification Authority — Advanced Chip Design

The mandate

The design-intelligence vice president was dismissed after a congestion-prediction model changed verification priorities without a reproducible training snapshot or approved feature revision. Tape-out was protected through manual review, but teams cannot prove which model influenced several closed design decisions. The assurance committee has suspended autonomous recommendations in physical-design workflows until qualified lineage and release control are established.

The interim must begin within twenty-one days and lead the function for ten months. The first two months reconstruct model use and create a safe operating baseline; qualification then expands across placement, routing, timing and verification analytics. A permanent search begins after the incident look-back, with six weeks reserved for successor shadowing before the non-extendable term expires.

Handover requires every production recommendation to resolve to design context, dataset snapshot, feature code, model artefact, tool version and accountable human disposition. Four priority pipelines must pass drift, reproducibility, fallback and unseen-design qualification, while two tape-out cycles operate without an unapproved model change. The successor will approve a release from raw evidence and sign the residual automation limits.

The interim may disable models, freeze features, redirect qualified compute, set release gates, engage temporary validation experts and commit the approved ₩14 billion remediation envelope. Any relaxation of human review, material change to design methodology, permanent hire, new EDA platform or tape-out-risk acceptance requires the engineering chief and assurance committee. The role may not certify silicon functionality or override designated sign-off owners.

Core EDA replacement, foundry commercial negotiations and model research unrelated to active design decisions are outside this mandate. The authority does not own chip architecture, product scheduling or historical experiments never used in a consequential flow. Pipeline qualification must remain focused on traceable recommendations and their human integration rather than turning into a general AI laboratory rebuild.

Why this seat is open

The untraceable change revealed that sophisticated models had acquired operating influence without corresponding release discipline. The dismissal created an immediate signing and prioritisation gap during live programmes. A temporary executive must restore design-team confidence, complete the forensic record and leave a permanent leader with qualified pipelines whose boundaries are understood before autonomy expands again.

What you will own

• Reconstruct which model versions, features and datasets influenced active designs, linking recommendations to engineer decisions and downstream verification evidence.
• Establish qualification tiers based on recommendation consequence, human review, novelty of design context and reversibility before tape-out.
• Decide which pipelines may return to assisted use, remain in shadow mode or be withdrawn until stronger evidence becomes available.
• Govern immutable dataset, feature, model, container, EDA-tool and design-context lineage through build, evaluation, approval, deployment and rollback.
• Direct unseen-design, corner-case, drift, reproducibility and fallback tests with thresholds agreed by methodology and product-assurance owners.
• Allocate scarce accelerator and licensed-tool capacity between remediation, live programme support and qualification without jeopardising sign-off workloads.
• Transfer release authority through a successor-led qualification review, two tape-out retrospectives and written acceptance of unresolved automation constraints.

Candidate qualifications

• Led ML platform or design-automation systems inside advanced semiconductor development, with accountable exposure to tape-out or product-assurance decisions.
• Qualified models influencing physical design, verification, test or yield and can explain why generic offline accuracy was insufficient evidence.
• Reconstructed an ML recommendation from immutable design context, features, training assets, artefacts and toolchain versions after a control failure.
• Established human-review and fallback boundaries for machine recommendations whose errors could consume material verification time or threaten schedule.
• Governed accelerator, EDA licence and sensitive design-data capacity across competing programmes under strict access and export constraints.
• Handed a recovered engineering-systems function to a permanent executive with qualification debt and limits on autonomous use explicitly recorded.

Non-negotiables

• Available within twenty-one days for a primarily Seoul-based exclusive assignment with planned work at validation and foundry interfaces.
• Has directly governed ML inside semiconductor design workflows; generic enterprise MLOps leadership will not satisfy the technical threshold.
• Will protect design intellectual property and observe all applicable export, foundry-access and segregated-compute requirements.
• No undisclosed remuneration from EDA, accelerator, model-platform or engineering-services suppliers involved in the remediation.

1. 49 words maximum. State your Seoul availability and one semiconductor design decision whose ML lineage you were accountable for.
2. 49 words maximum. How did you qualify a model on unseen designs when historical benchmark accuracy looked stronger than production behaviour?
3. 49 words maximum. Which artefacts must be immutable to reconstruct a machine recommendation that influenced physical design?