Advanced-Node Physical-Design Closure Leader — Network Processors

The mandate

The implementation director departed after three late engineering-change cycles fixed top-corner timing while reopening dynamic voltage-drop, congestion and hold failures elsewhere in a large network processor. Architecture continues changing traffic accelerators, package models arrive on a different cadence and sign-off tools disagree on parasitic and variation assumptions. The interim leader must restore convergent closure without declaring success by narrowing modes, corners or activity beyond product reality.

Thirteen months provide the recovery and tape-out window. The first six weeks freeze evidence definitions, reconcile netlist and constraint baselines and rank closure mechanisms. Months two through seven stabilise floorplan, clocking, power delivery and block interfaces. Months eight through eleven complete sign-off and tape-out. The final two months cover post-tape-out learning, permanent-leader installation and transfer of first-silicon implementation actions.

Handover is achieved when all approved modes and corners close timing, power integrity, physical verification and test requirements on one reproducible release baseline; ECO churn remains below threshold for six weeks; and the successor leads a seeded sign-off discrepancy. They must defend every waiver and package assumption to the steering committee. Hidden constraint deletion, unjustified false paths and untraceable manual database edits cannot enter the closure record.

The leader may freeze implementation netlists, control ECO intake, set sign-off tools and versions, allocate compute, redirect engineers and commit ₹15 crore within the authorised closure envelope. They chair tape-out readiness and may stop release pending evidence correction. Architecture features, foundry selection, product frequency commitments, package commercial agreements and final executive tape-out approval remain with established accountable leaders.

Excluded are redesigning the full processor architecture, owning RTL functional verification, negotiating EDA enterprise licences or promising first-silicon performance beyond approved sign-off evidence. The mandate covers physical implementation convergence and trustworthy release custody. IP disputes, employment investigations and customer schedule remedies remain outside the interim authority, even when their timing affects closure pressure.

Why this seat is open

Advanced-node closure is a coupled optimisation problem in which a local timing win can worsen routing, power, variation or manufacturability. The departure removed the only executive able to control ECO demand and arbitrate inconsistent sign-off assumptions across teams. Temporary leadership can force a stable evidence baseline now and leave a successor who has personally defended the release.

What you will own

• Reconcile RTL handoff, netlists, constraints, libraries, extraction decks, package models, activity and sign-off versions under release custody.
• Stabilise floorplan, hierarchy, macro placement, routing resources, clock architecture and power grid against real traffic modes.
• Govern setup, hold, variation, crosstalk, voltage-drop, electromigration, thermal and physical-verification closure as coupled evidence.
• Establish ECO intake, impact analysis, ownership, cut-off dates and rollback so late fixes cannot create invisible regression.
• Resolve block-to-top discrepancies in timing budgets, interface constraints, power intent, DFT logic and physical abstracts.
• Direct EDA compute and specialist effort toward root mechanisms rather than repeated brute-force runs or dashboard cosmetics.
• Transfer waiver rationale, unresolved margins, reproducible release scripts, first-silicon watchpoints and successor-led sign-off decisions.

Candidate qualifications

• Led physical implementation and sign-off of a large advanced-node processor or networking SoC through production tape-out.
• Can evidence a late timing fix that exposed a coupled power, routing, variation or package failure.
• Understands floorplanning, clocking, static timing, extraction, power integrity, physical verification, DFT and package interaction.
• Has controlled engineering-change demand from architecture and RTL leaders during an unstable closure window.
• Reconciled tool and corner disagreement without deleting legitimate modes or relying on undocumented manual edits.
• Developed a successor able to challenge waivers and stop tape-out despite material schedule pressure.

Non-negotiables

• Will lead onsite in Hyderabad and attend all Bengaluru and San Jose sign-off sessions.
• Has personally chaired advanced-node tape-out closure for a complex production processor.
• Accepts no unilateral authority over architecture scope, foundry choice, customer frequency promises or final tape-out approval.
• Will disclose EDA, IP, foundry, package and network-processor customer relationships before appointment.

1. 49 words maximum. Which late closure improvement caused the most damaging regression in another sign-off domain?
2. 49 words maximum. How would you prove a false path or waiver reflects product intent rather than schedule convenience?
3. 49 words maximum. What seeded discrepancy must the successor find before inheriting closure authority?