Director of Yield Engineering — Interim, Semiconductor Devices

The mandate

A mixed-signal device has remained at sixty-one per cent final yield through three ramp quarters, and the founding yield director exited after repeated unverified screen changes. Customer forecast now assumes volumes the current loss distribution cannot support.

The interim must begin within four weeks for twelve months, after which the role transfers to an internal principal engineer promoted into leadership. The final six weeks will test that successor through an independent yield council.

Handover requires final yield above eighty-eight per cent for sixteen consecutive weeks, no material increase in early-life failure, all screen changes statistically justified, and the successor independently approving two process-change experiments.

The director may prioritise analysis lots, set hold criteria and approve experiments within the yield budget. Permanent specification change, customer notification and equipment capital above ₹2 crore need governance approval; yield cannot override Quality disposition or mask fails through retest.

Next-generation architecture, sales allocation and unrelated mature-product cost reduction are excluded. The team must solve the named ramp and establish reusable analytical discipline.

Why this seat is open

Low yield persisted because correlation was repeatedly treated as cause and screens shifted faster than learning accumulated. Leadership exit allows a reset toward controlled experimentation. A temporary director will reach economic yield and prepare the strongest internal technical leader to own the system.

What you will own

• Decompose loss by wafer, assembly, test insertion, bin, equipment, material and temporal signature.
• Decide the highest-value causal experiments using statistical power, learning cycle and production risk.
• Establish golden-lot, split-lot and control-wafer protocols with immutable hypotheses and acceptance rules.
• Approve screen changes only after separating defect escape, test correlation and false rejection.
• Correlate yield recovery with reliability and customer-return evidence before sustaining each fix.
• Publish a weekly yield waterfall showing validated cause, experimental result and remaining opportunity.
• Qualify the internal successor through two independently chaired process-change councils.

Candidate qualifications

• Eighteen-plus years in semiconductor yield, product or process engineering across wafer and back-end test.
• Led a device ramp from sub-economic yield to stable high-volume performance.
• Advanced competence in statistical experimentation, defect pareto, test correlation and failure-analysis methods.
• Evidence of rejecting apparent yield gains caused by retest, screen relaxation or mix distortion.
• Experience coordinating foundry, OSAT, design and customer-quality teams around one causal fact base.
• Capability to develop an expert individual contributor into an accountable yield leader.

Non-negotiables

• Available onsite in Hyderabad within four weeks for engineering-lot and analysis cycles.
• Independent of foundry, OSAT and equipment suppliers connected to the ramp.
• Will not accept screen relaxation as yield improvement without reliability proof.
• Commits to twelve months and the internal-successor qualification period.

1. 49 words maximum. Confirm your start date and availability around controlled engineering-lot windows.
2. 49 words maximum. What device yield did you raise, from which baseline to which sustained result?
3. 49 words maximum. Which apparent yield gain did you reject because it merely shifted escapes or retest?