Board Strategy Adviser — Fabless Semiconductor Portfolio

The mandate

The board keeps returning to whether limited design capital should deepen one defensible product family or fund adjacent chips sought by early customers. Roadmaps currently understate verification capacity, software burden and foundry concentration.

Three days monthly include a portfolio review, technical-commercial challenge and committee attendance. A tape-out or IP-licence question receives acknowledgement within twenty-four hours and a reasoned view within four business days.

The twelve-month appointment spans the next architecture and funding cycle and is non-renewable. The adviser holds no line authority, tape-out approval, investment vote or executive responsibility.

Only two other semiconductor appointments may continue, neither with a direct product rival. Foundry, EDA, IP, customer and investor relationships must be fully declared, with recusal where non-public roadmaps overlap.

Why the board wants this voice

The founders are technically strong and understandably attached to product breadth. Investors need challenge from someone who has funded design cycles through qualification and commercial ramp. The missing voice connects architectural choices with cash, ecosystem leverage and customer concentration.

What you will own

• Test each product thesis against validated design wins, software readiness and reachable production economics.
• Challenge roadmap concurrency where verification or physical-design capacity is the true constraint.
• Press leaders on foundry allocation, node choice and second-source realism.
• Shape investment questions around reusable IP, differentiation and licence dependency.
• Examine customer-funded features for roadmap capture and concentration risk.
• Guide the committee's evidence gates for architecture freeze, tape-out and production funding.
• Advise when a product family should be paused to protect the core franchise.

Candidate qualifications

• 22–28 years in semiconductor product, architecture, business or investment leadership.
• Direct accountability for at least three chip programmes from definition through production ramp.
• Experience deciding process node, foundry, IP and portfolio trade-offs under constrained capital.
• Working command of verification, software enablement, yield learning and design-win conversion.
• Board credibility with technical founders and institutional investors.
• No undisclosed economic interest in relevant foundries, EDA or IP providers.

Non-negotiables

• Three Bengaluru days monthly across the architecture and funding cycle.
• Twenty-four-hour acknowledgement of documented tape-out decisions.
• Complete foundry, vendor, customer, investor and competitor disclosure.
• No operational design direction or authority to commit company capital.

1. 49 words maximum. Which semiconductor portfolio decision did you change, and what design-win or capacity evidence drove it?
2. 49 words maximum. List foundry, EDA, IP, investor or chip-company interests this board must assess for conflict.
3. 49 words maximum. Can you protect three monthly days and respond to a tape-out query within one day?