Coherent-Optical DSP Verification Director — Subsea Communications

The mandate

A coherent-modem ASIC passes block verification but diverges from floating-point performance under long-haul dispersion, nonlinear interference and rapid channel recovery. Fixed-point saturation and adaptation timing are distributed across blocks, optical models use favourable noise assumptions and firmware patches compensate without traceable algorithm intent. The defined problem is to establish executable end-to-end verification evidence for deployed subsea conditions before silicon release.

The deliverables are an impairment-model qualification, floating-to-fixed trace, numerical error budget, end-to-end reference chain, adaptation and acquisition scenarios, FEC interface evidence, error-injection suite, hardware-emulation plan, optical-laboratory correlation and accepted release dossier. Every result must bind algorithm, coefficients, precision, RTL, firmware, channel model and test seed. Unsupported model simplification requires alternate evidence.

Four milestones govern six months: model, precision and coverage-gap baseline by 30 October 2026; approved reference chain and impairment suites by 18 December; witnessed RTL, emulation and optical-loop correlation by 19 February 2027; and accepted closure argument, residual limits and client-led rerun by 31 March. Milestone evidence includes failed acquisition, cycle slips and extreme fixed-point traces.

Acceptance requires algorithm teams to reproduce numerical budgets, verification to close seeded corner failures, optical engineers to validate laboratory correlation and product leaders to own declared operating limits. The sponsor returns one consolidated verification-defect register within six working days. Passing average bit-error rate cannot satisfy acceptance when acquisition time, rare saturation, FEC cliff or recovery after abrupt impairment remains untested.

The client provides algorithms, floating and fixed models, RTL, firmware, channel data, emulation access, optical loops, FEC definitions, laboratory staff and controlled cable-system scenarios. It funds agreed model and test expansion. The director cannot release silicon, set customer reach claims, change cable operating policy or expose proprietary algorithms outside authorised environments.

Why this is external work

Algorithm, RTL and optical teams each see performance through different numerical and physical reference points. Existing owners also created the simplifications and workarounds now requiring independent challenge. An external director can connect end-to-end evidence and finish when client engineers reproduce the full model-to-laboratory closure without consultant-controlled assets.

What you will own

• Reconcile floating algorithms, fixed-point specifications, RTL, coefficients, firmware and channel-model versions under release custody.
• Qualify dispersion, noise, nonlinear, polarisation, frequency, phase and component impairment models against measured links.
• Build numerical budgets for quantisation, truncation, saturation, adaptation error, coefficient update and block interaction.
• Direct acquisition, tracking, cycle-slip, fault, abrupt-change and degraded-channel verification through end-to-end reference chains.
• Connect DSP output, soft information, FEC behaviour and post-correction margin around cliff and rare-event conditions.
• Correlate simulation, emulation and optical-loop results with declared reference planes, instrumentation and uncertainty.
• Deliver closure evidence, unsupported limits, regression assets, lab correlations and client-led release rehearsal.

Candidate qualifications

• Directed coherent optical DSP or high-speed communications silicon verification from algorithm through laboratory modem evidence across multiple hardware generations.
• Can evidence a fixed-point or adaptation defect hidden by favourable average link performance.
• Understands coherent receivers, equalisation, carrier recovery, nonlinear impairment, numerical precision, FEC and channel modelling.
• Has connected floating models, RTL, firmware, emulation and optical laboratories under controlled configuration.
• Challenged reach or performance claims when rare recovery and numerical tails remained unverified.
• Leaves executable regressions and client-owned models rather than a consultant-specific analysis environment.

Non-negotiables

• Will attend Sydney, Melbourne and Tokyo verification and optical-system sessions.
• Has personally closed coherent modem silicon against production-relevant optical impairments.
• Accepts milestone rejection when fixed-point, firmware, channel or test-seed configuration is not reproducible.
• Will disclose DSP IP, EDA, optical-equipment, cable-system and semiconductor relationships before engagement.

1. 49 words maximum. Which fixed-point defect remained hidden by strong average optical-link performance?
2. 49 words maximum. How would you correlate a nonlinear channel model with a controlled optical loop?
3. 49 words maximum. What rare recovery condition must be closed before coherent silicon release?