Take a look inside the world’s largest discreet leadership platform for manufacturing and industrials311 open mandates35 countriesEverything manufacturing leaders need

Confidential mandate

SVP – Engineering — Data-Centre Silicon Platform

Urgent / New

SVP – Engineering mandate in Austin, USA · Semiconductor

Lead engineering integration for a US data-centre silicon platform where silicon, package, board, firmware and workload evidence must converge before scale.

The mandate

A US data-centre silicon platform is ramping a complex product whose performance and customer deployment cross silicon, package, power delivery, board, firmware and workloads. Functional teams optimise their own metrics, but integration challenges move between layers and wafer yield does not fully predict system performance. A new SVP – Engineering will own integrated technical delivery.

Approximately 650 employees and material partners span silicon, product, package, systems, firmware, validation and customer engineering. The SVP owns engineering delivery, technical integration, failure learning and talent and reports to the Group Chief Executive or sponsor. Quality retains independent release.

The recovery will define the failing population precisely. Wafer location, package build, thermal condition, firmware, workload and test version must remain linked. Correlation will guide experiments but cannot become root cause without controlled evidence.

Yield should be measured at customer-usable performance and reliability, not only good die. Binning, power, memory and system screening may change effective supply. Engineering will align metrics and avoid shifting fallout downstream.

Experiment capacity is scarce. The SVP will prioritise splits by information value, preserve controls and stop unstructured debug. Changes require effectivity through inventory, systems and customer samples.

Customer collaboration will state sample status, limitations and next evidence. Confidential information between customers remains segregated. Security and firmware updates continue throughout recovery.

The role is new because no current engineering leader spans all layers. The onsite Austin appointee may redesign integration governance while preserving deep functional authority.

Advanced packaging and thermal behaviour need independent workstreams connected to silicon learning. Warpage, interconnect, power delivery and cooling can create intermittent signatures that escape standard test. The SVP will ensure physical analysis and system telemetry reach a common investigation without prematurely attributing fault to another partner.

Test strategy must evolve with root-cause understanding. Additional screens may protect customers temporarily but reduce capacity and create false rejects. Engineering will define containment, escape risk and retirement evidence for each screen and will not count screened yield as intrinsic process recovery.

Supplier collaboration requires controlled data rooms and decision rights. Foundry, package, memory and board partners may each need evidence without receiving another party’s confidential process information. Technical meetings will record hypotheses, experiments and owners, preventing duplicated trials and ambiguous responsibility.

Customer workload diversity matters. A benchmark can pass while a particular memory, security or power sequence exposes weakness. The SVP will prioritise representative workloads, document limitations and build telemetry into evaluation systems. Field observations will be preserved with configuration and sample genealogy.

Engineering culture must favour early contradiction. Reward and reviews will recognise people who disprove an attractive theory or halt an unsafe sample. Repeated escapes and late discoveries will prompt changes to design review, verification and integration ownership, not only individual corrective action.

Reliability planning will connect accelerated stress to customer conditions. Package, memory, voltage and thermal combinations need justified acceleration models and sample sizes. The SVP will ensure a passing laboratory test is not extrapolated beyond its evidence and will retain raw data for later field comparison.

Re-spin decisions require a clear threshold. Workarounds, screens, firmware limits and design change each carry schedule, capacity and lifecycle consequences. Engineering will present options and uncertainty to the sponsor, preserve quality independence and stop cumulative temporary controls from becoming an undocumented product baseline.

Talent deployment will build cross-layer capability through rotations and chaired investigations. Specialists remain deep in their fields, but integration leaders must learn enough package, system and customer context to recognise when a functional answer is incomplete.

What you will own

  • Lead integrated yield and system-ramp engineering.
  • Connect silicon, package, board, firmware and workload genealogy.
  • Prioritise experiments and technical resources.
  • Govern change, effectivity, sample status and root-cause evidence.
  • Align yield to customer-usable output.
  • Coordinate foundry, packaging and customer technical partners.
  • Protect security and lifecycle obligations.
  • Build engineering leadership and succession.

The first 12 months

In the first 30 days, define the major failing populations, reconcile metrics and establish one experiment and customer-sample governance. Protect urgent customer programmes.

By month six, close priority root causes, stabilise package and system interactions and reduce uncontrolled experiments. Strengthen integration leadership and technical succession.

At twelve months, improve customer-usable yield by ten points, reduce repeat failure signatures by 50% and deliver 95% of protected validation gates. Root-cause cycle time should fall 35%. No customer deployment should rely on an undisclosed sample limitation or known uncontained issue.

What the sponsor will measure

  • Yield expressed as usable qualified system output.
  • Failures traced across silicon and system layers.
  • Experiments selected for learning value.
  • Changes controlled through customer effectivity.
  • Technical communication precise during uncertainty.
  • Integrated leadership without weakening specialist authority.

The person

You bring 22–28 years in data-centre silicon, product, package or systems engineering, including yield ramp. You have led cross-layer root-cause recovery and customer qualification.

Your prior scope should include 450 engineers and partners or a major advanced-node product. Evidence must include a misleading average-yield metric, package-system interaction and experiment portfolio. Board and customer technical credibility are required.

Compensation and terms

Base compensation is US$320,000–420,000 plus annual incentive linked to usable yield, customer gates, technical learning and leadership. This permanent onsite Austin role reports to the Group Chief Executive or designated sponsor. The live ramp requires prompt availability.

Confidentiality

The platform, product, yield data, customers, suppliers and technical findings remain confidential. Detail follows fit, conflicts and signed confidentiality. Applicants must not contact ecosystem partners to infer the enterprise.

More seats like this one

Every live mandate, by seat →

This mandate is confidential. The client is named only under a mutual NDA, and your own record is never listed, sold or shown to a company under your name until you release it for this specific mandate.