Display-Driver IC Yield Recovery Leader — Augmented-Reality Microdisplays

The mandate

The display-silicon director left after high-resolution microdisplay builds showed column banding, grey-level compression and line-timing artefacts that vary across wafer lots and panel interfaces. Electrical wafer test passes many affected dies, while panel calibration removes visible mura at the cost of dynamic range and power. The interim leader must recover physical and visual yield without allowing per-unit correction to hide unstable driver silicon or interconnect.

Ten months provide the recovery window. The first six weeks secure die and panel genealogy, reproduce visual signatures and establish shipment containment. Months two through six close reference, column, timing, supply and interface mechanisms and redesign wafer tests. Months seven through nine qualify corrected lots and bounded calibration. The final month installs a permanent leader and transfers foundry, panel and release decisions.

Handover is achieved when electrical and visual yield meet approved distributions across three wafer and panel lots for eight consecutive weeks, calibration consumption stays below threshold and field-relevant patterns pass. The successor must chair one die-lot disposition, approve a calibration-limit change and defend residual uniformity evidence to product leadership. Selected images and hand-tuned lookup tables cannot count as stable output.

The leader may quarantine dies and panels, stop integration builds, approve design and test priorities, set calibration limits inside product specifications and commit ₹10 crore within the authorised recovery envelope. They decide driver readiness after product-quality consultation. Display architecture, optical-engine design, customer image claims, product pricing and long-term foundry or panel awards remain with accountable executives.

Excluded are redesigning the complete headset, changing human-factors requirements, owning panel fabrication, approving consumer launch or replacing all display electronics. The mandate covers driver IC physical yield, visual correlation and production control for the selected microdisplay family. Warranty policy, supplier liability and public product claims remain outside interim authority.

Why this seat is open

Microdisplay yield is determined by how precision analogue columns, timing, supplies, die interconnect and panel pixels combine in the human-visible image. The departure left silicon and display teams optimising electrical and visual definitions separately. Temporary leadership can contain poor lots now and leave a successor with measured limits on calibration rather than attractive corrected images.

What you will own

• Reconcile wafer lot, die position, package or bond, panel, timing, supplies, calibration version and visual-test genealogy.
• Connect reference, DAC, column, line-driver, clock and power variation to banding, mura, greyscale and motion artefacts.
• Build electrical monitors and patterns that predict integrated visual loss before expensive panel assembly.
• Separate silicon, interconnect, panel, optics, measurement and calibration contributions through controlled cross-builds.
• Govern calibration around correction range, dynamic-range loss, power, ageing, memory and factory cycle time.
• Direct foundry and panel suppliers through mechanism-based containment, corrective action, qualification and deviation expiry.
• Transfer failure signatures, wafer screens, calibration limits, open lots and successor-led release evidence.

Candidate qualifications

• Led display-driver, image-sensor or precision mixed-signal silicon yield from wafer test through visual product integration at production scale.
• Can evidence a visible defect that passed conventional electrical die testing and later correlated to controlled panel evidence.
• Understands column drivers, references, DACs, timing, supply integrity, display calibration and visual-uniformity measurement.
• Has reduced dependence on per-unit correction by recovering physical design or production controls.
• Directed foundry, package, panel and product teams through shared die-to-image genealogy.
• Developed a successor able to reject attractive calibrated output when underlying margin remains unstable.

Non-negotiables

• Will lead onsite in Chennai and attend all Bengaluru and Seoul silicon and panel reviews.
• Has personally released high-resolution display or imaging silicon against integrated visual evidence.
• Accepts no authority over headset launch, human-factors requirements, product claims or long-term awards.
• Will disclose foundry, display-panel, calibration, optics and augmented-reality relationships before appointment.

1. 49 words maximum. Which visible display defect escaped electrical wafer test, and why?
2. 49 words maximum. How would you prove calibration is correcting variation rather than hiding an unstable population?
3. 49 words maximum. What must the successor demonstrate before inheriting driver-lot release authority?