Leading-Edge Fab Yield-Ramp Leader — High-Performance Computing Silicon

The mandate

The yield executive left after successive lots showed correlated contact resistance, edge-die systematic loss and unstable high-frequency bins just as the flagship compute product entered customer qualification. Module owners are optimising local metrics, product engineering distrusts inline indicators, and operations continues releasing starts against a revenue plan that assumes a steeper learning curve. The interim leader must impose one yield truth without confusing normal advanced-node variation with an uncontrolled excursion.

Eighteen months provide a bounded ramp window: the first sixty days establish containment, golden-route discipline and loss paretos; months three through eight close priority mechanisms and rebuild learning-lot governance. Months nine through fourteen convert gains into capacity-qualified process windows across two sites. The final four months prove sustained output through customer mix changes, appoint a permanent leader and transfer supplier, equipment and design-interface decisions.

Handover is achieved when electrical and functional yield remain above the approved entitlement trajectory for twelve consecutive weeks, excursion escape time meets threshold, and predicted wafer-out reconciles to actual good die by product bin. The successor must chair two cross-site yield councils, approve one process-window change and defend remaining systematic loss to the ramp committee. Deferred experiments and masked scrap cannot be rebased out of the final record.

The leader may hold lots, change learning-wafer allocation, set split priorities, require tool matching, reassign integration resources and commit TWD 900 million within the authorised ramp envelope. They decide production release after documented product and reliability consultation. Customer specification changes, major capital purchases, product pricing, design respins and permanent site-volume allocation remain with the named executives and established change boards.

Excluded are redesigning the processor architecture, taking ownership of fab-wide cost, certifying long-term reliability or replacing the manufacturing execution platform. The mandate concerns physical yield learning, stable process windows and accountable ramp decisions for the selected family. Patent conclusions, supplier litigation and customer compensation stay with legal and commercial leaders, supported by preserved technical evidence.

Why this seat is open

Advanced-node learning stalls when every function can explain its own chart but nobody owns the economic good-die outcome. The departure created an immediate authority gap at the point where experimental freedom must narrow into repeatable production. A temporary executive can make contested holds and resource choices now while building a successor who inherits verified mechanisms rather than optimistic forecasts.

What you will own

• Establish one loss taxonomy connecting inline defects, parametric distributions, wafer sort, final test, reliability screens and customer-relevant bins.
• Direct mechanism-based paretos across patterning, deposition, etch, clean, implant, contact and interconnect modules without rewarding metric displacement.
• Govern learning lots, split design, sample size, control wafers and decision dates against scarce cycle-time and tool capacity.
• Reconcile design sensitivities, process corners and test guard-bands so physical improvement is not hidden by shifting bin definitions.
• Tighten excursion detection through tool genealogy, chamber matching, spatial signatures, material lots and rapid containment authority.
• Convert demonstrated yield movement into credible wafer-start, good-die, cycle-time and customer-commitment forecasts for executives.
• Transfer the mechanism library, open hypotheses, equipment dependencies, supplier actions and witnessed ramp governance to the successor.

Candidate qualifications

• Led advanced-logic yield or process-integration ramps from engineering lots into high-volume manufacture at demanding geometries.
• Can evidence a systematic loss mechanism isolated through combined inline, electrical, spatial and product-performance data.
• Understands patterning variability, transistor and interconnect interactions, tool matching, design-technology co-optimisation and statistical learning limits.
• Has made costly lot-hold or experiment-priority decisions while revenue, customer qualification and cycle time were under pressure.
• Directed cross-site teams without allowing local process ownership to fragment the product-level yield objective.
• Developed a permanent yield leader able to challenge design, equipment and manufacturing executives with reproducible evidence.

Non-negotiables

• Will lead from the Hsinchu fab and attend all published Tainan and San Jose reviews.
• Has personally recovered a leading-edge production ramp, not only supported technology-development yield analysis.
• Accepts no unilateral authority over product specifications, design respins, customer commercial terms or major capital approval.
• Will disclose foundry, equipment, materials, EDA and processor-customer relationships before appointment.

1. 49 words maximum. Which correlated yield signature led you to a mechanism that local module metrics had obscured?
2. 49 words maximum. What evidence would justify holding revenue-critical wafers during an uncertain advanced-node excursion?
3. 49 words maximum. What must a successor demonstrate before inheriting release authority for a live ramp?