Three-Dimensional NAND Process-Window Recovery Leader — Enterprise Storage

The mandate

The integration vice-president departed after the newest stacked NAND generation showed lower-string current, staircase contact loss and widening threshold distributions that escaped pilot lots but appeared under volume tool mix. Product teams compensated with programme algorithms and guard-bands, obscuring physical yield and reducing endurance margin. The interim leader must recover the manufacturable window across extreme aspect-ratio modules without treating controller correction as an unlimited process concession.

Twelve months form the recovery window. The first six weeks secure suspect lots, align cross-section and electrical paretos, and define an honest good-array baseline. Months two through six resolve channel etch, film uniformity, wafer bow and staircase mechanisms. Months seven through ten qualify matched tool populations and product algorithms. The final two months prove volume stability, install a permanent integration leader and transfer remaining generation risks.

Handover is achieved when array yield, programme distribution and endurance margin hold above approved targets across all qualified tool groups for ten production weeks. The successor must chair a high-aspect-ratio excursion, approve one integration split and reconcile process movement with controller compensation before the product council. Hidden redundancy consumption, engineering-only tool selection and excessive bad-block allowance cannot count as stable recovery.

The leader may hold wafer lots, change integration targets inside approved design limits, allocate engineering chambers, prioritise destructive analysis and commit KRW 7 billion within the recovery envelope. They decide process release after documented reliability and product consultation. Cell-architecture changes, controller firmware release, new-fab capital, customer warranty policy and long-term equipment awards remain with the established design, product and operations executives.

Excluded are owning the whole memory roadmap, redesigning error-correction algorithms, replacing factory automation or attributing contractual liability to an equipment supplier. The mandate covers physical process-window recovery for the specified generation and its transfer into mixed-tool volume. Intellectual-property disputes and customer commercial actions remain outside the interim’s authority, supported by protected technical facts.

Why this seat is open

High-layer-count NAND multiplies small depth, profile and film variations into electrical distributions that no module can solve alone. The leadership departure left process teams optimising local signatures while product guard-bands silently absorb yield and lifetime. A temporary integration executive can force physical mechanism closure now and leave a permanent owner with proven mixed-tool capability.

What you will own

• Connect channel profile, bow, film thickness, staircase alignment and contact integrity to string current and threshold distributions.
• Establish physical-loss paretos that expose redundancy use, bad-block masking and controller compensation rather than accepting apparent final yield.
• Govern splits across etch depth, deposition uniformity, anneal, wafer stress and contact modules with sufficient cross-tool replication.
• Direct failure analysis using cross-section, materials, electrical localisation and array-pattern evidence tied to exact wafer genealogy.
• Qualify equipment populations through chamber matching, consumable life, maintenance state and product-corner response.
• Reconcile process limits with programme algorithms, endurance, retention and read-disturb so recovery does not borrow future reliability.
• Transfer qualified windows, unresolved mechanisms, supplier obligations, monitoring limits and successor-led release decisions.

Candidate qualifications

• Led 3D NAND integration or yield recovery through high-layer-count technology development and volume manufacturing.
• Can evidence a channel, staircase or film mechanism hidden by redundancy, controller adjustment or engineering-tool selection.
• Understands extreme aspect-ratio etch, multilayer deposition, wafer stress, cell distributions, endurance and product algorithm interactions.
• Has made contested holds and equipment-allocation choices during a revenue-critical memory ramp.
• Directed destructive physical analysis and electrical characterisation with traceable wafer, chamber and consumable genealogy.
• Developed a successor capable of defending physical yield against pressure to solve every excursion in firmware.

Non-negotiables

• Will work onsite across the Icheon and Cheongju production and equipment-review cadence.
• Has personally recovered volume 3D NAND integration, not only modelled memory devices or designed controllers.
• Accepts no unilateral authority over controller release, cell architecture, warranty treatment or factory capital expansion.
• Will disclose memory producer, equipment, materials and enterprise-storage customer relationships before appointment.

1. 49 words maximum. Which 3D NAND mechanism remained hidden longest behind redundancy or controller compensation?
2. 49 words maximum. What proves a recovered process window will survive a mixed production tool population?
3. 49 words maximum. Which decision must the successor execute before receiving integration release authority?